Export 12 results:
Sort by: Filters: Author is Hsu, Chung-hsing [Clear All Filters]
"Green Supercomputing in a Desktop Box",
3rd IEEE Workshop on High-Performance, Power-Aware Computing (in conjunction with the 21st International Parallel & Distributed Processing Symposium), Long Beach, California, March, 2007.
"Making a Case for a Green500 List",
2nd IEEE Workshop on High-Performance, Power-Aware Computing (in conjunction with the 20th International Parallel & Distributed Processing Symposium), Rhodes, Greece, April, 2006.
"A Feasibility Analysis of Power Awareness in Commodity-Based High-Performance Clusters",
7th IEEE International Conference on Cluster Computing (CLUSTER'05), Boston, Massachusetts, September, 2005.
"A Power-Aware Run-Time System for High-Performance Computing",
ACM/IEEE SC2005: The International Conference on High-Performance Computing, Networking, and Storage, Seattle, Washington, November, 2005.
"Effective Dynamic Voltage Scaling through CPU-Boundedness Detection",
Lecture Notes in Computer Science, February, 2005.
"When Discreteness Meets Continuity: Energy-Optimal DVS Scheduling Revisited",
Los Alamos, February, 2005.
"Reducing Overheating-Induced Failures via Performance-Aware CPU Power Management",
6th International Conference on Linux Clusters: The HPC Revolution 2005, April, 2005.
"Towards Efficient Supercomputing: A Quest for the Right Metric",
1st IEEE Workshop on High-Performance, Power-Aware Computing (in conjunction with the 19th International Parallel & Distributed Processing Symposium), Denver, Colorado, April, 2005.
"Towards Efficient Supercomputing: Choosing the Right Efficiency Metric",
IEEE International Parallel & Distributed Processing Symposium (IPDPS) Workshop on High-Performance, Power-Aware Computing, April, 2005.
"Green Destiny and Its Evolving Parts",
Innovative Supercomputer Architecture Award, 19th International Supercomputer Conference, Heidelberg, Germany, June, 2004.
"The Origin and Evolution of Green Destiny",
IEEE Cool Chips VII: An International Symposium on Low-Power and High-Speed Chips, Yokohama, Japan, April, 2004.
"{The Design, Implementation, and Evaluation of a Compiler Algorithm for CPU Energy Reduction}",
PLDI 2003: ACM SIGPLAN Conference on Programming Language Design and Implementation, June, 2003.
